EDGE

Backside power sparks an architectural gamble. Intel's PowerVia routes power to front M0 (debug-friendly, less scaling). TSMC's A16 SPR sends power direct to bottom S/D, seeking performance. Extreme alignment aside, frees front space for ultimate scaling, ensuring strongest PPA.

BPD relies on extreme wafer-flipping: temp carrier support; DISCO grinds 99% Si to micron thickness; IR alignment etches nano TSVs for front contacts; low-temp backside power layer deposition. This micro-refinement sparks huge opportunities for semi equipment makers.

Traditional front-side power delivery crowds signals & power, causing crises: thick lines take >20% space, hindering miniaturization; current via ultra-thin wires causes severe IR Drop, degrading performance & heat. The sole solution is to move the power delivery network to the wafer backside, fu...

GAA hasn't solved chip scaling's wiring congestion: traditional top-side power/signal causes IR Drop near 2nm, limiting performance. Backside Power Delivery Network (BSPDN) moves power to wafer's backside, separating power/signals. This engineering is critical for TSMC A16 vs. Intel 18A.

Samsung rushed 3nm GAA to overtake, but suffered Waterloo due to low etching yield & immature ecosystem. TSMC maximized FinFET, secured high-yield orders, steadily introduced 2nm GAA, proving mature ecosystem true moat. 1nm angstrom transistors will adopt vertically stacked P/N CFET, initiating f...

GAA is nanoscale Jenga. Epitaxially stacking Si/SiGe builds framework; trenches cut. Lam Research's "selective etching" removes SiGe sacrificial layers, suspending Si nanosheets. ASMI's ALD fills metal gates in narrow gaps. Gravity-defying, it challenges GAA yield.