EDGE

/ 135 posts
5-2-1 CoWoS Architecture Universe: Photomask Limits and TSMC's Process Magic
Semiconductor
EDGE / / 20 minutes read

5-2-1 CoWoS Architecture Universe: Photomask Limits and TSMC's Process Magic

TSMC's CoWoS resolves AI chip bottlenecks, tackling thick substrate signal loss. It uses silicon interposers as micro-highways for high-density TSV/lithography. The article details CoW/oS processes, explaining TSMC's high-value dominance and substrate assembly outsourcing. This precision engineer...
5-1-11 The Final Battle: The Red Wolf Pack Under the City Walls and a Panoramic Map of Semiconductor Packaging
Semiconductor
EDGE / / 3 minutes read

5-1-11 The Final Battle: The Red Wolf Pack Under the City Walls and a Panoramic Map of Semiconductor Packaging

Semiconductor packaging & testing competition analyzed. Chinese 'red-chip' firms (JCET, Tongfu, Unisilicon) challenge traditional giants via asymmetric strategies. Tech mapping from traditional to 3D heterogeneous integration shows packaging evolving to extend Moore's Law via 'brain surgery.' Thi...
5-1-10 OSAT Giants' Counterattack Defense Line: ASE Technology Holding (ASE) and Amkor's VIPack
Semiconductor
EDGE / / 10 minutes read

5-1-10 OSAT Giants' Counterattack Defense Line: ASE Technology Holding (ASE) and Amkor's VIPack

OSAT firms counter TSMC's lead & China's price wars. ASE builds a moat via LEAP/VIPack, with flexible capacity & heterogeneous integration. Amkor targets high-end auto/US clients; Powertech focuses on HBM. All shift to system integration, pursuing AI breakthroughs.
5-1-9 The Vanishing Boundaries of Business Warfare: TSMC's Dimension-Reduction Strike
Semiconductor
EDGE / / 7 minutes read

5-1-9 The Vanishing Boundaries of Business Warfare: TSMC's Dimension-Reduction Strike

TSMC's InFO blurs foundry/OSAT lines. Its nanoscale process launched a 'dimension-reduction strike,' eliminating substrates for ultra-thinness. Co-design linked front/back processes, overcame bottlenecks, built high tech barriers/customer stickiness, reshaping semiconductor competition.
5-1-8 The 'Disintegration' and Rebirth of Moore's Law: The Additive Magic of Chiplets and Yield
Semiconductor
EDGE / / 8 minutes read

5-1-8 The 'Disintegration' and Rebirth of Moore's Law: The Additive Magic of Chiplets and Yield

Moore's Law faces miniaturization's reticle/yield. Chiplet tech disassembles large chips; heterogeneous integration reassembles varied parts, yield additive (vs. mult.) cuts costs. AMD MI300 shows 3D packaging/UCIe key for post-Moore compute.
5-1-7 The Spatial Reversal: The Performance Revolution of RDL and Flip Chip (Flip Chip Packaging)
Semiconductor
EDGE / / 9 minutes read

5-1-7 The Spatial Reversal: The Performance Revolution of RDL and Flip Chip (Flip Chip Packaging)

Flip Chip's spatial reversal breaks wire bonding bottlenecks. RDL routes contacts from edge to interior; copper pillars connect directly to substrate, reducing latency, increasing bandwidth, optimizing cooling. Despite thermal expansion warping (needs underfill), it's crucial for AI chip compute ...