1-3-2 The Three Unavoidable Mountains

Foreword: Silicon Valley's Most Crowded VIP Room

Under the spotlight of the semiconductor industry, people see NVIDIA's surging stock price and discuss TSMC's advanced manufacturing processes. However, in the shadow of this vast empire, there is an absolute power that controls every pulse from 0 to 1.

If TSMC masters the atomic arrangement of the physical world, then the EDA (Electronic Design Automation) triumvirate—Synopsys, Cadence, and Siemens EDA (Siemens, formerly Mentor Graphics)—masters the logical soul of the digital world.

This is not a free-competition market. Over 90% of the global EDA market share is carved up by these three companies. This is an "iron-fisted oligopoly" formed after four decades of brutal mergers and acquisitions and desperate patent battles.

In this field, there is no room for a fourth player to survive; and in the arena of cutting-edge processes (3nm, 2nm), they are gods holding the power of life and death.

Chapter One: The Three Kingdoms — Maps and Territories

Although the three giants now all claim to offer "end-to-end" solutions, tracing back their technological DNA reveals that each occupies an unshakeable stronghold.

1. Synopsys: Digital Overlord and Compiler of Logic

• Ticker: SNPS
• Market Position: The market leader, the "Microsoft" of the EDA industry.
• Core DNA: Digital Synthesis.

Synopsys's rise stemmed from solving a fundamental problem: "How to automatically convert human-written code into logic gates?" In the 1980s, it launched the groundbreaking product Design Compiler. This is like the "Google Translate" of the chip world, capable of translating high-level languages (HDL) into logic gate netlists.

Why is it unshakeable? Design Compiler remains the absolute standard for digital chip design worldwide. When Intel, NVIDIA, and Apple have accumulated thirty years of legacy code optimized based on Synopsys's syntax rules, the cost of switching EDA tools is no less than changing a country's official language. Synopsys thus monopolizes the foremost entry point for CPU, GPU, and AI chips.

2. Cadence: Analog Master and Artist of Simulation

• Ticker: CDNS
• Market Position: The second-largest player in the market, but with "religious-like" loyalty in specific domains.
• Core DNA: Analog Design and Mixed-Signal.

If the digital world is a strict sequence of 0s and 1s, then the analog world (dealing with sound, light, radio waves) is the quantum mechanics full of noise and variables. Cadence's Virtuoso platform is the "bible" for analog engineers worldwide. From Wi-Fi chips to power management ICs, almost all are born on Cadence's platform.

Furthermore, Cadence is extremely strong in packaging design and PCB (Printed Circuit Board) fields. As Moore's Law slows down, advanced packaging (CoWoS, Chiplet) has become a prominent trend, and Cadence, with its deep accumulation in physical layers, is becoming a leader in the "post-Moore's Law era."

3. Siemens EDA (formerly Mentor Graphics): Verification Gatekeeper

• Ticker: SIE (part of the Siemens Group)
• Market Position: Acquired by German industrial giant Siemens in 2017, becoming a core piece of its "digital twin" strategy.
• Core DNA: Physical Verification.

Mentor Graphics (now Siemens EDA) possesses a trump card that makes the entire industry bow down—Calibre. In the "Sign-off" process mentioned in the previous chapter, Calibre is the industry-recognized "gold standard."

Dominance: There is an unwritten rule in the industry: "Sign-off with Calibre." Even if you used Synopsys for layout and Cadence for simulation, at the final moment of submitting to TSMC for production, TSMC typically only accepts the pass issued by Calibre. This is because Calibre's algorithms are most precisely calibrated with TSMC's mask manufacturing equipment, and no one dares to risk chip failure by using other tools.

Chapter Two: Deep Deconstruction — Four Moats

Why have these three companies maintained their dominance for 40 years? Why are even companies like Google and Apple, with unlimited resources, unwilling to develop their own EDA tools, choosing instead to pay hundreds of millions of dollars in "protection money" annually? The answer lies in four unassailable moats.

Moat One: PDK — The Blood Pact with Foundries

This is the most difficult mechanism for outsiders to understand, yet it is at the very core of the EDA oligopoly.

What is a PDK (Process Design Kit)? Imagine TSMC invents a brand-new 3nm process. The physical limits, transistor characteristics, and resistor-capacitor parameters of this process must be communicated to IC design companies so they can design chips. TSMC doesn't send a PDF manual to MediaTek; instead, it releases a massive, encrypted database—this is the PDK.

Formation of the Oligopoly: In the early stages of developing a 3nm process (approximately 2-3 years before mass production), TSMC invites engineers from Synopsys and Cadence to its fabs. Both parties collaborate on development and calibration to ensure that the EDA software can perfectly read and interpret this PDK.

• Lock-in Effect: When TSMC announces 3nm mass production, only the software from these three giants can "understand" TSMC's PDK.
• Entry Barrier: If a new EDA startup wants to enter the market, it cannot obtain TSMC's PDK certification; without certification, no IC design client would dare to use it; without clients, it cannot obtain data. This is a perfect death spiral.

Moat Two: The M&A Machine — Devouring All Innovation (The Pac-Man Strategy)

The growth history of the EDA industry is a history of mergers and acquisitions, where big fish eat small fish.

Because chip design involves numerous stages (from logic, physical, verification to testing), a single startup can often only achieve breakthroughs in a small segment (a Point Tool) (e.g., an AI-driven layout tool). Once a small company demonstrates a threat or possesses unique technology, the three giants' strategy is highly consistent: buy it and integrate it into their platform.

• Synopsys has conducted over 100 acquisitions to date.
• Siemens' acquisition of Mentor itself was one of the largest software acquisitions in industrial history.

This strategy has created a "Swiss cheese effect": the platforms of the three giants are like a solid block of cheese, where startups can only survive in the holes; once a hole gets larger, it is filled (acquired).

Moat Three: IP Licensing — Originally Just Selling Shovels, Now Selling Bricks Too

Synopsys and Cadence don't just sell design software; they are now among the world's largest IP (Intellectual Property) providers (second only to ARM).

• Strategy: When you design a chip, you need USB interfaces, DDR memory controllers, and PCIe interfaces. These standard modules don't need to be reinvented.
• Bundling: Synopsys will tell you: "Buy my EDA software, and while you're at it, buy my USB IP. I guarantee these two will work perfectly together, and integration will be the fastest."
• This "software + building blocks" bundled sales approach significantly increases customer stickiness.

Moat Four: Hardware Emulation — Expensive Artillery

Referring back to the "big refrigerator" (Emulator) we mentioned in the previous chapter. Developing such specialized supercomputers requires extremely strong hardware design capabilities and supply chain management. This goes beyond the scope of typical software companies. This has allowed the three EDA giants to evolve from pure software vendors into "hardware-software integrated" system behemoths, further raising the bar for competition.

Chapter Three: Geopolitical "Nuclear Button" (The Choke Point)

Before 2018, EDA was seen as a paradigm of globalized division of labor; but with the outbreak of the US-China tech war, EDA instantly became the most precise and lethal weapon in America's hands.

Why EDA?

• Equipment (DUV/EUV) is hard to ban: Equipment is physical, and older equipment can be repaired and circulated in the secondhand market.
• Software (EDA) is easy to disable: EDA operates on a license model, typically requiring online verification or periodic key updates. With just a single ban from the US Department of Commerce, manufacturers stop sending update keys, and the software automatically expires once the license runs out.

GAAFET's Dimensional Attack: In 2022, the US announced a ban on the export of EDA software supporting GAA (Gate-All-Around) architecture to China. This move is extremely malicious. This is because for processes below 3nm, the traditional FinFET architecture becomes ineffective, necessitating a transition to GAA.

• Without EDA software supporting GAA, engineers cannot create physical models for 3D transistors.
• This means that even if China acquires lithography machines and resolves material issues, on the design end, the door to 3nm is directly welded shut.

Conclusion: The Semiconductor World's "Tax Office"

The oligopoly of the three EDA giants is not merely commercial hegemony; rather, it is a high wall built upon the "complexity of physical limits" and "supply chain trust."

In this field, "old" is the greatest asset.

• Forty years of algorithm accumulation.
• Forty years of foundry data calibration.
• Forty years of customer usage habits.

These three companies are like the "definers of physical laws" in the semiconductor world, and also the "tax office" collecting tribute from the entire industry.

For investors or observers, understanding the position of Synopsys, Cadence, and Siemens EDA means understanding why, even though the semiconductor industry experiences intense cyclical fluctuations, the stock prices of these three companies can consistently reach new highs, navigating both bull and bear markets.

Because no matter who wins the AI war (NVIDIA or AMD), and no matter who wins the foundry war (TSMC or Intel), the winners must first pay EDA before celebrating.