The Three Core Theses from the Earnings Call

Before delving into the detailed data from this earnings call, we believe investors must first understand the historical turning point TSMC currently finds itself in. The signals released during this meeting confirmed the following three structural arguments:

1. The Victory of Pricing Power: Redistribution of Supply Chain Profit Pools

In past semiconductor cycles, foundries were often constrained by customer inventory adjustments. However, in the current AI race, we observe a rare phenomenon: while downstream fabless design companies face pressure to lower end-product prices, and major IDM companies are deeply mired in transformation losses, TSMC's gross margin has defied the trend, soaring and stabilizing above the 60% mark. What does this mean? It indicates that TSMC, leveraging "capacity scarcity" and "technological exclusivity," has successfully shifted the profit center of the semiconductor value chain from design to manufacturing.

2. The Declaration of Capital: An "Absolute Barrier" Erected with $56 Billion

Management announced an increase in 2026 capital expenditure (CapEx) to the range of $52 billion to $56 billion. The market should not view this merely as an expense, but rather as a "pre-acquisition" of the industry landscape for the next three years. What does this mean? Under such an enormous financial barrier, there are no substantive challengers remaining in the advanced process technology realm. TSMC is using scale to raise the cost of advancing Moore's Law to a dimension unreachable by competitors.

3. The Shift in Risk: From Commercial Competition to Physical Limits

With Intel and Samsung falling behind in advanced process technology, TSMC's biggest threat has shifted. Future risks no longer stem from product iterations by commercial competitors, but rather from constraints of the physical world (limits of power supply) and variables of the political world (geopolitical tug-of-war). What does this mean? Investors' monitoring indicators must change—less focus on competitor yield news, and more on Taiwan's power grid reserve capacity and global energy policies.

Table of Contents

Part One: Executive Summary — The Starting Point for AI Demand "Monetization"

1. Core Thesis: AI Demand "De-bubbling" and "Monetization" Verified
2. Financial Landscape Deconstruction: Redefining Pricing Power and Profit Structure
3. Capital Expenditure (CapEx) Strategy Analysis: An "Insurmountable Barrier" Built with $56 Billion
4. Strategic Turning Point and New Risk Normal: Constraints of the Physical World
5. Investment Outlook: Long-term Structural Bull

Part Two: Financial Decoding — Reshaping the Profit Structure in an "Absolute Seller's Market"

1. Revenue Quality Analysis: From "Wafer Foundry" to "Compute Solutions"
2. The Underlying Logic of the 60% Gross Margin New Normal (Pricing Power, Economies of Scale, Exchange Rates)
3. Health of Free Cash Flow (FCF) and Dividend Commitment

Part Three: Demand Deep Dive — Seeing Through "Customers' Customers": The True Nature of AI Demand

• Chapter One: The Transparency Revolution — Why Can TSMC See Through the Supply Chain Mist?
• Chapter Two: The Cloud Battlefield (Cloud) — From "Arms Race" to "Realization and Deployment" (Training & Inference)
• Chapter Three: The Edge Battlefield (Edge) — The Silent Giant of H2 2026 (AI PC/Smartphone)
• Chapter Four: The Dividends of Physical Complexity — CoWoS, Chiplet, and Reticle Limits

Part Four: Technology Moat — The "Dual-Track" Hegemony of the Angstrom Era

• Chapter One: Decoding Technical Terms (Nanosheet / N2 / N2P / A16 / SPR)
• Chapter Two: Commercial Strategy Segmentation — A Complete "Solution Menu" (A16 for Pinnacle Performance vs. N2P for Volume)
• Chapter Three: Latest Progress and Yield Updates — The High-Speed Operation of an "Execution Machine"

Part Five: Risk Dashboard — From "Commercial Competition" to "Systemic Constraints"

1. Red Alert: Power Supply in Taiwan — A Hard Constraint on Growth
2. Yellow Alert: Global Operating Costs and Geopolitics (China+1)
3. Green/Yellow Alert: The Talent War
• Appendix: Essential Risk Monitoring Checklist for Investors

Part Six: Supply Chain Linkage Mapping — Discovering "Hidden Champions" Under the TSMC Colossus

• Tier-1 Core Circle: Equipment and Key Subsystems (EUV Mask Pods / CoWoS Equipment / Inspection)
• Tier-2 Operating Circle: Materials and Chemicals (Photoresist / Specialty Gases / Reclaimed Wafers)
• Tier-3 Derivative Circle: Infrastructure and Green Energy (Heavy Electrical Equipment / Grid Strengthening)

Part Seven: Conclusion and Recommendations — Standing on the Shoulders of Giants

1. Historical Positioning: The "General Electric (GE)" of the AI Era and Infrastructure Attributes
2. Valuation Paradigm Shift
3. Ultimate Investment Strategy: Core and Satellite Allocation Method
4. Concluding Remarks: Embracing the "Inevitable" Future

【Disclaimer】 This report is for reference only and does not constitute an offer or invitation to buy or sell any securities. Investors should make independent judgments and bear their own risks.

Part One: Executive Summary — A Leap from "Cyclicality" to "Rigid Infrastructure"

1. Core Thesis: AI Demand "De-bubbling" and "Monetization" Verified

This 2025 Q4 earnings call was not just the announcement of excellent financial results; it also marked a critical psychological threshold for the global semiconductor industry—a shift from fear of an AI bubble to confirmation of AI's substantial returns on investment (ROI).

Over the past year, the market has had doubts about the sustainability of massive capital expenditures by Cloud Service Providers (CSPs). However, the information released by TSMC's management during this call, especially regarding insights into "customers' customers," provided strong counter-evidence. We observed the following qualitative changes:

• Authenticity of Demand: Order drivers no longer solely stem from market share anxiety (Fear of Missing Out, FOMO), but rather from real cash flows generated by end-user applications (such as inference services, precise advertising, and enterprise AI assistants).
• Diffusion of Demand: AI compute demand is rapidly spilling over from the singular "model training" phase to the much larger and more sustained "inference" phase. This means chip demand will no longer be pulsed, but rather a long-tail, rigid demand akin to electricity.

Against this backdrop, TSMC's role has evolved from traditional "manufacturing foundry" in electronics cycles to an indispensable "Core Computing Infrastructure" in the AI era. Its valuation model should gradually detach from the framework of traditional semiconductor inventory cycles and move towards a long-term growth model with a strong moat.

2. Financial Landscape Deconstruction: Redefining Pricing Power and Profit Structure

TSMC's 2025 Q4 EPS of NT$19.5 and full-year EPS of NT$66.25, coupled with a Q1 2026 gross margin guidance as high as 63-65%, reveal an extremely rare industry phenomenon.

Why can ultra-high gross margins be maintained despite high depreciation? Typically, a significant expansion in capital expenditure (CapEx) is accompanied by depreciation pressure, which in turn suppresses gross margins. However, TSMC has defied this rule, primarily due to the establishment of its "absolute pricing power":

• Extreme Seller's Market: Currently, in 3nm and more advanced processes (N2), as well as CoWoS advanced packaging, there is no second source globally with comparable mass production capabilities. This allows TSMC to pass on inflation and expansion costs in contracts, and even capture a scarcity premium.
• Astonishing Yield Curve Efficiency: The initial yield and output of 2nm (N2) mass production exceeded expectations, significantly shortening the learning curve and enabling new processes to reach their profit sweet spot faster.
• Structural Mix Optimization: The revenue mix continues to shift towards high-priced High-Performance Computing (HPC), effectively offsetting some of the seasonal fluctuations in mature processes or consumer electronics.

Data Implications: Estimated dollar revenue growth for 2026 is nearly 30%, far exceeding the average level for the semiconductor industry (excluding memory). This implies that TSMC is "eating up" most of the industry's profit increments, and the Matthew Effect of the strong getting stronger is intensifying.

3. Capital Expenditure (CapEx) Strategy Analysis: An "Insufferable Barrier" Built with $56 Billion

Management announced a significant increase in 2026 capital expenditure to $52 billion - $56 billion. We believe investors should interpret this figure from a strategic perspective:

• Scale as a Moat: This scale of expenditure already surpasses the total semiconductor division revenue of most competitors (such as Intel, Samsung). This means that the advanced process competition is no longer a technology race, but an ultimate showdown of "capital efficiency" and "cash flow capability." TSMC is using a massive financial barrier to make potential challengers despair over their financial models, thereby effectively ending the competition for generations below 2nm.
• Order Locking Effect: Approximately 70-80% of this enormous investment is allocated to advanced process technologies. This implicitly involves long-term agreements (LTAs) and advance payment mechanisms with customers. In other words, this $56 billion expenditure, to some extent, corresponds to confirmed future revenues, rather than blind capacity expansion.
• Supply Chain Redistribution: The massive expenditure will directly reshape the upstream equipment and materials supply chain. Key segments such as EUV lithography machines, advanced packaging equipment (Bonder/Sorter), and inspection and measurement equipment will enter a super cycle lasting 3-5 years.

4. Strategic Turning Point and New Risk Normal: Constraints of the Physical World

Despite an optimistic outlook, this earnings call clearly pointed out the limits to growth—no longer insufficient market demand, but rather a shortage of physical resources.

• Power Constraint: CEO C.C. Wei uncharacteristically and frankly expressed his "deepest concern about the power supply in Taiwan." This signals that "energy supply" has surpassed "commercial competition" in TSMC's operational risk model. As the energy consumption for manufacturing AI chips rises exponentially (due to increased EUV layers and higher process complexity), power stability will directly determine the upper limit of production capacity.
• Cost of Globalization: With the Arizona fab (Fab 21) in the US and the Kumamoto fab (JASM) in Japan commencing production, TSMC formally enters the era of "global manufacturing." While this reduces single-point geopolitical risk, it will inevitably lead to higher management costs and a structural dilution of overall gross margins (though currently appearing manageable).

5. Investment Outlook (Strategic Allocation View)

Based on the analysis above, we maintain a "Long-term Structural Bull" outlook for TSMC.

• Portfolio Allocation: Given its monopolistic position in the AI value chain and high visibility of profitability, TSMC should be regarded as a Core Defensive Growth Asset in an investment portfolio.
• Key Monitoring Points: Investors should not overreact to monthly revenue fluctuations or short-term geopolitical noise. Future monitoring should shift towards:
  1. N2 and A16 mass production yield ramp-up progress (whether technological leadership is sustained).
  2. Status of power supply in Taiwan and implementation of green energy policies (whether production capacity is constrained).
  3. Expansion speed of advanced packaging (CoWoS/SoIC) (whether backlog can be met).

Summary: TSMC is at the strongest point in its corporate lifecycle. It not only holds the key to the AI era but has also secured this key for the next 3-5 years through a dual moat of capital and technology, ensuring no one can take it away.

Part Two: Financial Decoding — Reshaping the Profit Structure in an "Absolute Seller's Market"

In the long history of the semiconductor industry, we rarely see a manufacturing enterprise (Foundry) announce record-high capital expenditures ($52 billion - $56 billion) while simultaneously providing market-stunning gross margin guidance (63-65%).

This seemingly contradictory set of data (high expenditure vs. high profitability) reveals that TSMC's financial model has undergone a structural qualitative change. We should no longer use the traditional "capacity utilization" model to evaluate TSMC, but rather a "Value-based Pricing" model.

1. Revenue Quality Analysis: From "Wafer Foundry" to "Compute Solutions"

TSMC's 2025 Q4 revenue beat expectations, not from a broad recovery across all products, but from the contribution of "extremely high-purity" advanced process technologies.

• HPC Dominance: High-Performance Computing (HPC) platforms now account for over 55% of revenue. This means TSMC has effectively detached from the risk of a single engine like smartphones, transitioning to a data-center-centric growth structure.
• Structural Uplift in ASP (Average Selling Price):
  • Process Premium: The 3nm (N3) series processes became the main revenue driver in 2025, with significantly higher wafer prices than 5nm. As 2nm (N2) ramps up in 2026, according to supply chain sources, the initial pricing for N2 is expected to reach new highs (estimated to increase by 15-20% compared to N3).
  • Packaging Premium: CoWoS advanced packaging is no longer an "ancillary service" but a "core product." As chips adopt Chiplet designs, the complexity and value of packaging increase exponentially. TSMC not only sells wafers but also integrated services, which substantially increases the implicit value of each wafer sold.

2. The Underlying Logic of the 60% Gross Margin New Normal

Why did gross margin reach a new high at the moment of greatest depreciation pressure? This was the most striking aspect of this earnings call for institutional investors. We summarize three supporting points:

• Absolute Pricing Power: In the N2 and A16 generations, TSMC is the sole global supplier. This grants it absolute ability to counter inflation and rising costs. In the past, it was "customers cutting prices," now it's "customers bidding for capacity." Long-term agreements (LTAs) generally include stricter price protection clauses and advance payment mechanisms.
• Economies of Scale and Yield Curve: C.C. Wei explicitly stated that the N2 yield ramp-up was extremely smooth. This benefits from the accumulated learning experience during the long lifecycle of N3. When yields reach high standards in the initial stages of mass production, it means reduced scrap rates and rapidly decreasing unit costs, directly contributing to gross profit.
• Exchange Rate Boost and Asset Utilization Efficiency: Although the earnings call did not focus much on exchange rates, a strong US dollar is beneficial to TSMC's revenue. More importantly, TSMC has effectively diluted the depreciation impact of newly acquired equipment by reusing some depreciated mature process equipment and by optimizing the production efficiency of existing EUV machines to their limits (increasing throughput).

3. Health of Free Cash Flow (FCF)

Investors' greatest concern is whether massive CapEx would cripple cash flow and impact dividend payouts.

• EBITDA Umbrella: Although CapEx is as high as $56 billion, TSMC's estimated EBITDA (earnings before interest, taxes, depreciation, and amortization) growth is even more astonishing. Robust operating cash flow (OCF) is sufficient to fully cover capital expenditure and maintain positive free cash flow (FCF).
• Dividend Policy Commitment: The CFO explicitly hinted that the dividend policy would remain "sustainable and steadily increasing." This demonstrates the company's high confidence in its cash recovery capabilities for the next few years.

Part Three: Demand Deep Dive — Seeing Through "Customers' Customers": The True Nature of AI Demand

"We don't just talk to our customers; we listen to our customers' customers." — C.C. Wei

Chapter One: The Transparency Revolution — Why Can TSMC See Through the Supply Chain Mist?

In past semiconductor cycles, a common risk was the "Bullwhip Effect"—downstream buying slightly more leads to frantic upstream expansion, resulting in inventory disasters. But this time is different.

• Direct-to-End-User Dialogue Mechanism: C.C. Wei's mention of "power dialogues" in the earnings call confirms that TSMC has established direct strategic communication channels with Hyperscalers (cloud giants). TSMC not only knows how many orders Nvidia has placed but also how many data centers Microsoft plans to build and what Google's TPU iteration roadmap entails.
• CapEx as a Vote of Confidence: The $56 billion capital expenditure is essentially TSMC's vote of confidence in these end-user giants' "expansion plans for the next 3-5 years." Without seeing long-term contracts signed by end customers and concrete data center blueprints, it would be impossible for TSMC's management, with its consistently prudent style, to issue such an expenditure commitment.

Chapter Two: The Cloud Battlefield (Cloud) — From "Arms Race" to "Realization and Deployment"

The market's doubt about AI is: "Money has been invested, can it be recouped?" TSMC's answer is a resounding yes. We break down end-user demand into three stages:

1. Training: The Arms Race Continues Unabated

Although demand for GPT-5 level model training is widely known, growth in this area has not slowed.

• Exponential Expansion of Model Parameters: In pursuit of higher intelligence (AGI), the parameters and data volume of next-generation models continue to grow exponentially. This signifies an insatiable demand for "single-chip compute power" and "memory bandwidth."
• Sovereign AI: Beyond major US tech giants, governments worldwide (Europe, Middle East, Asia) are beginning to build their own foundational models. This represents a new and massive source of training demand, and this compute power ultimately points to TSMC's advanced process technologies.

2. Inference: The True Explosion Point of Massive Demand (Key Highlight of this Earnings Call)

C.C. Wei specifically emphasized that demand is shifting from Training to Inference. This is the core argument supporting TSMC's high growth over the next five years.

• Difference in Usage Frequency: "Training" is a one-time (or periodic) activity, but "inference" happens every second. When one billion users globally call Copilot ten times a day, the total compute power required will far exceed that for model training.
• Establishment of Business Models:
  • Microsoft: The Copilot subscription model has proven commercially viable, with accelerating enterprise penetration.
  • Meta: Through open-sourcing the Llama model, Meta is embedding AI into applications with billions of users like Instagram and WhatsApp, which requires immense inference compute power to support its advertising and recommendation algorithms.
  • Google: Deeply integrating Gemini into Search and Workspace means every search is an inference computation.
• Conclusion: The explosion of inference demand means AI chips will transform from "R&D equipment" into "operational consumables," and demand will possess the rigidity of utilities like water and electricity.

3. The Rise of Custom Chips (ASIC): TSMC's Double Insurance

In addition to purchasing Nvidia GPUs, cloud giants are independently developing their own chips (ASICs) to reduce costs and optimize specific model performance.

• Google TPU, AWS Trainium/Inferentia, Microsoft Maia, Meta MTIA.
• TSMC's Role: All (100%) of these ASICs are manufactured by TSMC.
• Strategic Significance: This is a huge positive for TSMC. Even if Nvidia's market share declines due to the rise of ASICs, TSMC's total order volume remains unchanged, and in fact, due to the fragmentation of ASIC designs, it is even more advantageous for TSMC to leverage its design services and IP ecosystem.

Chapter Three: The Edge Battlefield (Edge) — The Silent Giant of H2 2026

While cloud computing is currently the main revenue driver, TSMC management hinted that "Edge AI" is about to take over.

1. Catalyst for the Replacement Cycle

In recent years, the smartphone and PC markets have lacked innovation, extending replacement cycles. But "On-device AI" will change the rules.

• Privacy and Latency: For privacy protection and real-time response, future AI processing will adopt a "Hybrid AI" model, where some computations must be performed locally on phones or laptops.
• Brutal Hardware Specification Upgrades: To run 7B or 10B parameter models on a smartphone, the NPU (Neural Processing Unit) compute power must double, and DRAM capacity must also significantly expand.

2. TSMC's Sweet Spot: N2 and N2P

• Apple's Key Role: As TSMC's first N2 customer, Apple is expected to introduce A-series chips with powerful local AI capabilities in the iPhone 18 (tentative name). This will absorb TSMC's massive initial N2 mass production capacity.
• Non-Apple Camp Follow-up: The competition between Qualcomm and MediaTek in AI smartphone chips will drive N3P and N2P capacity utilization to remain full throughout 2026-2027.

Chapter Four: The Dividends of Physical Complexity — CoWoS and Chiplet

Finally, we must discuss the phenomenon of "chips getting larger." This is also an undeniable aspect of customer demand.

1. Breaking Through Reticle Limits

As Moore's Law slows, it becomes increasingly difficult to cram more transistors onto a single chip. Nvidia's Blackwell architecture already involves "two chips combined into one."

• Trend: Future AI chips (such as Nvidia Rubin, AMD MI400 series) will be larger, more complex, and employ more chiplets.
• Implications for TSMC:
  • Significant Increase in Silicon Content: An AI GPU may contain two compute dies, 8-12 HBM (High-Bandwidth Memory) stacks, and a bottom base die. All of these must be procured from or integrated by TSMC.
  • Packaging Becomes a Bottleneck and a Goldmine: Customers are now scrambling not just for wafer capacity, but for CoWoS packaging capacity. Due to extremely high technical barriers (difficulty in yield control), TSMC's pricing power for CoWoS is even greater than for wafer manufacturing itself.

2. SoIC: The Unique Weapon for Next-Generation Packaging

In addition to CoWoS (2.5D packaging), TSMC's SoIC (3D packaging) technology has begun to be adopted by AMD and Apple. This technology, which "vertically stacks" chips, can significantly increase transmission speed and reduce power consumption, making it a critical puzzle piece for maximizing A16 process performance. This further deepens customer reliance on the TSMC ecosystem (Lock-in Effect).

【Chapter Summary: The Moat of Demand】

Synthesizing the above analysis, we can see that TSMC's "customers' customers" are building an extremely vast and interconnected ecosystem:

1. Cloud giants, to monetize, must frantically build inference compute power.
2. Edge devices, to host AI functions, must upgrade to 3nm/2nm processes.
3. Chip designs, to break through physical limits, must rely on advanced packaging (CoWoS/SoIC).

These three segments, without exception, all converge on TSMC. This is why TSMC dares to invest $56 billion in capital expenditure, and why we believe its growth over the next three years possesses utility-like certainty.

Part Four: Technology Moat — The "Dual-Track" Hegemony of the Angstrom Era

As AI chip demand shifts from "quantity" to "quality," the evolution of process technology is no longer just about shrinking dimensions, but a complete architectural overhaul. In 2026, TSMC officially enters the "Angstrom Era."

To help investors understand why TSMC continues to monopolize high-end AI manufacturing, we must first decipher these key technical codes: Nanosheet (GAA), N2 vs. N2P, and the most revolutionary SPR (Super Power Rail).

Chapter One: Decoding Technical Terms — The Language Shift from Nanometer to Angstrom

1. Revolution in Underlying Architecture: From FinFET to Nanosheet (GAA)

For the past decade or so (from 16nm to 3nm), TSMC dominated with FinFET (Fin Field-Effect Transistor) technology. But by the 2nm generation, FinFET has reached its physical limits, and leakage current issues are difficult to control.

• What is Nanosheet (GAA)? Full name is "Gate-All-Around." This is the brand-new transistor architecture adopted by TSMC for the 2nm (N2) generation.
• Layman's Analogy:
  • FinFET (Old Era): Imagine a faucet where your hand (Gate) can only grip the pipe from three directions (left, right, top) to control water flow. When the pipe is too thin, water (current) easily leaks out from the ungripped fourth direction, causing phones to overheat and consume excessive power.
  • Nanosheet (New Era): TSMC suspends the pipe, allowing your hand to tightly enclose it from all directions (360 degrees).
• Investment Implications: This architecture maximizes current control, meaning chips run faster with the same power, or consume less power at the same speed. This is precisely the most sought-after metric for AI data centers—"Performance per Watt."

2. The N2 Family: Precise Positioning of N2 and N2P

Within the 2nm family, TSMC distinguishes between two sub-generations, which often confuses outsiders.

• N2 (2nm Baseline):
  • Definition: TSMC's first-generation process using the Nanosheet architecture.
  • Current Status: Entered High Volume Manufacturing (HVM) in Q4 2025, with a smooth yield ramp-up. It serves as the foundation for all subsequent technologies.
• N2P (2nm Performance):
  • Definition: The performance-enhanced version of N2.
  • Key Difference: Note that N2P still uses traditional "front-side power delivery" technology. This differs from competitors (such as Intel, which initially planned to rush the introduction of backside power delivery at 20A/18A).
  • Commercial Logic: TSMC chose to maintain "architectural stability" for N2P, not risking changes to the power delivery network. The goal is to provide this to customers who are more cost-sensitive and prefer not to undertake excessive technical risks (e.g., Apple's iPhone chips or MediaTek's Dimensity series). N2P is the sweet spot product that pursues both "cost-effectiveness" and "mass production stability."

3. A16 and SPR: The "Black Technology" of the Angstrom Era

A16 is TSMC's defined next-generation flagship process (equivalent to 1.6nm), expected to enter mass production in the second half of 2026. Its revolutionary nature stems from the introduction of SPR (Super Power Rail).

Core Decoding: What is SPR / Backside Power Delivery Network (BSPDN)?

This is TSMC's proprietary term for its Backside Power Delivery Network technology.

• Traditional Pain Point (Front-Side Power Delivery): Imagine a wafer as a skyscraper. In the past, "signal lines (small cars)" for data transmission and "power lines (large trucks)" for power delivery all crowded the top floor roads (front-side M0 layer of the wafer).
  • Consequence: As process technology scaled down, the roads narrowed, causing large trucks and small cars to compete for lanes, leading to traffic jams (increased resistance, signal interference), and hindering chip performance.
• SPR Solution (Backside Power Delivery): TSMC made a bold engineering decision—to send the large trucks to the underground tunnels.
  • Technical Implementation: The power lines (Power Rail) are moved to the backside of the wafer, directly supplying power to the transistors from underneath.
  • Benefits:
    1. Space Liberation: The front side (top floor) is no longer cluttered with large trucks, leaving all space for signal lines, significantly increasing wiring density (logic density).
    2. Clean Power Delivery: Current does not need to take circuitous paths, reaching the core directly. IR Drop (voltage drop) is greatly reduced, boosting chip speed.

🔍 Insight: Why did TSMC wait until A16 for SPR? Competitor Intel attempted to forcefully introduce backside power delivery (PowerVia) in the 2nm generation (20A), which resulted in yield and mass production schedule setbacks. TSMC adopted a more prudent strategy: "First, conquer the Nanosheet architecture with N2, then tackle SPR power delivery with A16." This phased approach significantly reduced mass production risks, which is why C.C. Wei confidently stated in the earnings call that A16 development is ahead of schedule.

Chapter Two: Commercial Strategy Segmentation — A Complete "Solution Menu" (Strategic Segmentation)

What is most striking about TSMC in the Angstrom Era is not only the depth of its technology but also the breadth of its product portfolio. Unlike competitors who often bet on a single technology node (One-size-fits-all), TSMC has precisely carved out two parallel tracks by combining the A16 and N2 families.

This is a "dual-track" business model designed to maximize market share and profit margins.

1. Pinnacle Strategy: A16 + SPR — Targeting "Cost-No-Object" AI Crown Jewels

• Product Positioning: Ultra-Premium.
• Core Technology: Combines Nanosheet transistor architecture + SPR (Super Power Rail) backside power delivery technology.
• Target Customers: HPC (High-Performance Computing) and AI data center chips.
  • Typical Representatives: NVIDIA's next-generation GPUs (e.g., successors to the Rubin architecture), AMD MI series, Google TPU v6/v7.
• Commercial Logic:
  • These customers are least sensitive to chip prices (Price Inelastic). For a GPU selling for $50,000, an additional $500 in chip cost is irrelevant; the key is that compute power and power efficiency must be world-leading.
  • Value of SPR: For these massive chips, SPR solves the most troublesome "power delivery bottleneck" and "signal congestion." This allows more transistors to be packed into the same area, boosting performance by 8-10% or more. This 10% performance increase, for data center operators, translates into billions of dollars in electricity savings and a competitive advantage.
  • Pricing Strategy: TSMC prices this process at the top of the pyramid, enjoying the highest gross margins to harvest the richest profits from the AI wave.

2. Mainstream Strategy: N2 / N2P — Securing the "Cash Flow" Baseline

• Product Positioning: Sweet Spot.
• Core Technology: Nanosheet transistor architecture, but maintaining front-side power delivery (no SPR).
• Target Customers: High-end smartphones (Mobile AP) and consumer PC processors.
  • Typical Representatives: Apple A-series chips (iPhone), Qualcomm Snapdragon, MediaTek Dimensity, Intel Lunar Lake series (partial outsourcing).
• Commercial Logic:
  • While smartphone chips also pursue performance, they are extremely sensitive to cost and mass production yield. The smartphone market sees annual sales of one billion units, and even a $10 increase in chip cost can have a huge impact on profit margins.
  • Why no rush for SPR? While backside power delivery is powerful, the process steps are complex and costs are very high. N2P, through optimized design, can already offer significantly stronger performance than N3P, and by maintaining front-side power delivery, it ensures a very fast yield ramp-up, meeting demand for tens of millions of smartphone chips.
  • Strategic Significance: N2/N2P is TSMC's "Cash Cow." It is responsible for filling vast capacity utilization, spreading depreciation costs, and providing a stable cash flow foundation for the company.

3. Competitive Comparison: TSMC's "Steady" vs. Intel's "Hasty"

The brilliance of this dual-track strategy lies in its stark contrast to competitor Intel.

• Intel's (18A) Bet: Intel attempted to simultaneously introduce two new technologies at the 18A node (equivalent to TSMC's N2): RibbonFET (i.e., Nanosheet) and PowerVia (i.e., backside power delivery).
  • Risk: Simultaneously changing the engine and chassis led to an explosion in process complexity, making yield ramp-up extremely difficult. This is why Intel's 18A mass production schedule has been repeatedly delayed and customer adoption slow.
• TSMC's Pace:
  • Step 1 (N2): First, change the engine (Nanosheet), keep the chassis unchanged. Ensure large-scale shipments in 2025.
  • Step 2 (A16): Once the engine is mature, then change the chassis (SPR). Ensure the strongest performance in 2026.
  • Result: TSMC can always provide customers with "predictable" and "high-yield" capacity. For customers who cannot afford to jeopardize their product launch times (such as Apple), TSMC is the only choice.

Chapter Three: Latest Progress and Yield Updates — The High-Speed Operation of an "Execution Machine" (Status Update)

Even the best strategy is useless without mass production capability. In this earnings call (Q4 2025), management's update on the latest progress across key nodes conveyed a clear signal: TSMC's advanced process mass production engine is operating at its most efficient state in history.

1. N2 (2nm) Family: Smooth Mass Production, Surprising Yields

N2 is TSMC's first battle in crossing into the Nanosheet architecture. The market originally anticipated a longer learning curve and slower yield ramp-up for the new architecture. However, CEO C.C. Wei provided an encouraging response during the earnings call:

• Mass Production Milestone Confirmed: N2 officially entered High Volume Manufacturing (HVM) in Q4 2025. This means that production lines at the Hsinchu Baoshan and Kaohsiung fabs have begun operating for launch customers like Apple.
• Yield Curve Exceeded Expectations: This was a technical highlight of the earnings call. Management revealed that N2's yield performance in the initial stages of mass production was "better than N5 (5nm) at the same stage."
  • Interpretation: Considering that N2 adopted a completely new transistor architecture (GAA) and still maintained such high yields, it demonstrates TSMC's mastery of new materials and process control has reached an impeccable level. This will significantly reduce depreciation burden in early 2026 and improve gross margin performance.
• N2P Takes Over: With the smooth mass production of N2, development progress for the performance-enhanced N2P has also accelerated, and it is expected to seamlessly transition, becoming the mainstream process for smartphones and HPC from H2 2026 to 2027.

2. A16 (Angstrom Era): On Schedule, Locking in AI Hegemony

Regarding the highly anticipated A16 and SPR technologies, management reiterated the timeline, dispelling rumors that "backside power delivery technology is too difficult and might be delayed."

• Timeline Locked: The goal of mass production in H2 2026 remains unchanged. This means TSMC will launch the more mature A16 product, verified by N2 mass production, within the same timeframe that Intel claims for its 14A mass production.
• Customer Engagement: C.C. Wei hinted that customer inquiries and design tape-outs for A16 are even more enthusiastic than they were for N2 at the time. This is primarily due to AI customers' insatiable demand for "compute density."
  • Subtext: NVIDIA's and AMD's next-generation flagship GPUs are almost certainly adopting the A16 process. This ensures TSMC's revenue growth momentum in 2027-2028.

3. CoWoS and SoIC: Breaking Packaging Bottlenecks

While this chapter primarily discusses process technology, it is essential to mention the progress in advanced packaging, as it has become a "prerequisite" for advanced process shipments.

• CoWoS Capacity: Management confirmed that CoWoS capacity in 2026 will again double compared to 2025, but even so, capacity remains "tight." This indicates that the demand for AI chips far exceeds the supply.
• SoIC (3D Packaging) Takes Off: In conjunction with the A16 process, the adoption rate of SoIC will significantly increase in 2026. This technology, which vertically stacks chips, will be a crucial enabler for A16 to achieve maximum performance.

【Part Four Summary: The Breadth of the Moat】

Synthesizing the analysis from the preceding three chapters, we can draw one conclusion: TSMC's technological moat has not narrowed; on the contrary, it is widening.

• Distance from Samsung: Samsung has struggled with 3nm GAA yields for a long time and has yet to gain the trust of major customers (such as Nvidia/Apple). TSMC's smooth N2 mass production declares that the gap between the two in terms of yield and capacity has widened to an irreversible extent.
• Distance from Intel: Intel attempted a "cornering overtake" with 18A, but in the face of TSMC's robust "dual-track" strategy with A16 and "better-than-expected" N2 yields, even if Intel can produce it, it will be hard to pose a substantial threat in terms of cost structure and mass production scale.

Investment Conclusion: In the semiconductor technology race of 2026-2028, TSMC has already secured its victory in advance.

Part Five: Risk Dashboard — From "Commercial Competition" to "Systemic Constraints" (Risk Dashboard)

As TSMC pulls ahead in technology and market share, we believe the nature of the risks it faces has fundamentally changed.

Past risks were "endogenous," such as inability to achieve yields or being outcompeted technologically. Current risks are "exogenous," stemming from physical world resource limitations (water and power) and geopolitical maneuvering.

To help investors quantify these variables, we have established the following "red, yellow, and green light" risk dashboard.

1. Red Alert: Power Supply in Taiwan — A Hard Constraint on Growth

This is undoubtedly the most serious warning issued by management during this earnings call. C.C. Wei's frank concern about the power supply in Taiwan means that energy supply is no longer just a cost item, but a capacity ceiling for expansion.

Why is it a Red Alert?

• "Energy Inflation" for AI Chips: The energy consumption to produce one AI chip is significantly higher than for traditional chips. As we enter the 2nm and A16 generations, the number of EUV (Extreme Ultraviolet) lithography layers greatly increases, and the introduction of backside power delivery in A16 requires more complex steps, leading to an exponential rise in power consumption per wafer.
• Dual Pressure from Green Energy: TSMC not only needs "power" but "green power." Major customers (Apple, Microsoft, Google) have all committed to RE100 (100% renewable energy). If the supply of green power in Taiwan is insufficient, TSMC will be unable to meet its customers' ESG requirements and may even face carbon tariff pressure.

Monitoring Indicators

• Reserve Margin Rate: Closely monitor whether Taiwan's reserve margin frequently drops below the 10% alert line during peak summer electricity demand.
• Progress of Major Power Plants: Whether the completion timelines for natural gas receiving terminals (third and fourth LNG terminals) and new gas-fired units are delayed.
• Policy Shift: Changes in Taiwan's energy policy regarding the extension of nuclear power plant operations will be a critical variable in alleviating medium-term power shortage pressure.

Analyst's View: While power issues may not cause production line shutdowns in the short term, they might force TSMC to accelerate some expansion plans overseas (e.g., to the US or Japan), which would indirectly lead to decreased capital expenditure efficiency and increased costs.

2. Yellow Alert: Global Operating Costs and Geopolitics

With the Arizona fab (Fab 21) and Kumamoto fab (JASM) gradually ramping up production, TSMC officially enters an era of "global manufacturing." This brings two major structural challenges.

A. Margin Dilution Risk

• Overseas Cost Premium: Management has repeatedly mentioned that the construction and operating costs of overseas fabs are significantly higher than in Taiwan (US fab costs are even 2-3 times higher than in Taiwan). As the proportion of overseas capacity increases, this will exert structural dilution pressure on overall gross margins.
• Mitigating Factors: TSMC mitigates this by "Strategic Pricing," passing on some costs to customers (e.g., if a customer requests production in the US, they must pay a higher price). Currently, customers generally appear willing to pay this premium due to supply chain resilience considerations.

B. Geopolitical "China+1" Pressure

• Customer Anxiety: While TSMC emphasizes that Taiwan is its R&D and manufacturing hub, some European and American customers (under government pressure or for their own hedging considerations) are accelerating demands for a "China+1" or "Taiwan+1" strategy, requiring a certain percentage of capacity to be located outside Taiwan.
• Potential Impact: If geopolitical tensions escalate, this "forced diversification" pressure will increase, potentially leading TSMC to undertake inefficient redundant investments overseas.

3. Green/Yellow Alert: The Talent War

• In Taiwan: Despite a serious declining birthrate, TSMC, as a top employer in Taiwan, can still attract the most talented STEM professionals. Currently, the talent supply appears relatively stable (Green Light).
• Globally: There is a more severe shortage of semiconductor engineers in the US and Germany. Additionally, union cultures (especially in Germany) pose a potential integration risk with TSMC's "accountability-based" culture. This requires continuous monitoring of employee turnover rates at overseas fabs and is currently classified as under observation (Yellow Light).

【Essential for Investors: Risk Monitoring Dashboard】

We recommend investors use the following table as a quarterly checklist for monitoring TSMC's risks:

【Chapter Summary】

For TSMC, "problems that can be solved with money (such as technology R&D, equipment procurement) are not problems." The real challenges lie in "problems that money cannot solve (such as power shortages, geopolitics)."

Investors, while enjoying the growth dividends brought by AI, must constantly monitor the "red alerts" mentioned above. This is why, while recommending long-term holding, we emphasize the need to pay close attention to infrastructure development in Taiwan.

Part Six: Supply Chain Linkage Mapping — Discovering "Hidden Champions" Under the TSMC Colossus (Supply Chain Mapping)

When TSMC announced that its 2026 capital expenditure would reach the astronomical figure of $52 billion - $56 billion, this was no longer just one company's expansion plan, but a global semiconductor supply chain "Spending Spree."

For investors, TSMC represents "stable Beta," while its underlying supply chain harbors "explosive Alpha." We decompose this multi-billion dollar procurement chain into three concentric circles based on "technological exclusivity" and "performance linkage."

Tier-1 Core Circle: Equipment and Critical Subsystems (Tier-1: Critical Equipment)

Suppliers in this tier possess "chokepoint" technologies indispensable for TSMC's advanced processes (N2/A16) and advanced packaging (CoWoS). Their performance shows a 1:1 high positive correlation with TSMC's CapEx.

1. EUV Ecosystem "Gatekeepers": Mask Pods and Pellicles

As N2 and A16 processes introduce High-NA EUV or increase exposure layers, the protection of photomasks becomes paramount.

• EUV Mask Pods:
  • Technical Barrier: EUV masks are extremely expensive (hundreds of thousands of dollars per piece) and highly sensitive to micro-dust. Mask pods must achieve "zero-defect" cleanliness and feature special anti-static and anti-vibration designs.
  • Market Landscape: This is a highly oligopolistic market, primarily shared by leading local manufacturers in Taiwan and US-based manufacturers. As TSMC's number of EUV machines surges, demand for mask pods will multiply.
  • Investment Logic: These are "consumable-type" equipment, with both new machine procurement demand and replacement demand for old pods, ensuring extremely stable cash flow.
• EUV Pellicles:
  • Technical Barrier: In the A16 process, EUV light sources are more powerful, and traditional pellicles are prone to burning out. New-generation "carbon nanotube" or "composite material" pellicles become essential. Manufacturers that can provide high-transparency and high-temperature-resistant pellicles will enjoy very high gross margins.

2. CoWoS Advanced Packaging "Arms Dealers"

C.C. Wei mentioned that CoWoS capacity will "double again," which directly triggered demand for packaging equipment. Unlike front-end processes monopolized by major US and Dutch manufacturers (Applied Materials, ASML), back-end packaging equipment is the main battlefield for local manufacturers in Taiwan.

• Wet Process Equipment:
  • Key Processes: Cleaning, Etching, Stripping.
  • Technological Evolution: As Chiplet stacking layers increase (e.g., SoIC), the difficulty of cleaning thinned wafers greatly increases, requiring higher precision single-wafer spin cleaning technology. Manufacturers in Taiwan have surpassed Japanese competitors in this field, becoming TSMC's preferred choice.
• Bonders and Bonding Equipment:
  • Key Processes: Precisely "attaching" GPUs, HBM, and substrates together.
  • Hybrid Bonding: This is the core technology for SoIC. Equipment precision requirements advance from micrometers (μm) to nanometers (nm). Manufacturers capable of providing high-precision TCB (Thermo-Compression Bonding) or hybrid bonding equipment are the biggest beneficiaries of this expansion wave.
• Automated Material Handling Systems (AMHS) and Wafer Carriers:
  • Scenario: Smart Fabs. CoWoS processes are intricate, and wafers need to move frequently between different machines, greatly increasing demand for Overhead Hoist Transport (OHT) and storage systems (Stockers).

3. Metrology & Inspection

In the A16 Angstrom era, transistor structures become 3D Nanosheets, and traditional optical inspection can no longer clearly see internal structures.

• E-beam Inspection: Demand surges for detecting microscopic defects invisible to the naked eye.
• MA/MI (Macro Inspection): As CoWoS package sizes grow increasingly large (greater than 4x reticle size), inspection for warpage and foreign objects after packaging becomes a rigid demand.

Tier-2 Operating Circle: Materials & Chemicals (Tier-2: Materials & Chemicals)

If equipment stocks profit from "expansion gains (one-time)," then material stocks profit from "operational gains (continuous)." As TSMC's capacity utilization reaches its peak, the consumption of these consumables will soar.

1. High-End Photoresist

• EUV Photoresist: Used to transfer circuit patterns onto wafers. Currently dominated by Japanese manufacturers (JSR, TOK, Shin-Etsu), but manufacturers in Taiwan have obtained certification for photoresist supporting materials (such as thinners, photoresist removers) and are gradually encroaching on the Japanese market share.

2. Specialty Gases

• Demand Scenario: Both etching and deposition processes require large quantities of specialty gases (e.g., neon, electronic-grade ammonia).
• Localization Advantage: Based on supply chain resilience and carbon footprint considerations, TSMC is actively fostering local electronic-grade gas suppliers in Taiwan to replace expensive imported gases. This provides an excellent opportunity for local chemical giants to transform.

3. Silicon Wafers and Reclaimed Wafers

• Reclaimed Wafers: The more advanced the process, the greater the consumption of "monitor wafers" and "dummy wafers" used to monitor machine status. To save costs, TSMC extensively uses reclaimed wafers (reusing used wafers after cleaning and polishing). Taiwan boasts the global's highest market share in the reclaimed wafer industry chain.

Tier-3 Derivative Circle: Infrastructure and Green Energy (Tier-3: Infrastructure)

This tier is not directly related to TSMC's chip technology but is closely tied to its "operating environment." This represents the largest derivative business opportunity stemming from C.C. Wei's "power anxiety."

1. Heavy Electrical Equipment and Grid Strengthening

• Transformers and Switchboards: Each new fab TSMC builds requires the establishment of an ultra-high voltage substation. This creates rigid demand for transformers (especially 345kV class).
• Uninterruptible Power Systems (UPS): The last line of defense against voltage sags that could lead to wafer scrap.
• Investment Logic: These heavy electrical equipment manufacturers benefit not only from TSMC but also from US grid modernization and Taiwan's grid strengthening program, featuring a "dual engine."

2. Green Power and Energy Storage

• RE100 Pressure: TSMC is the largest buyer of green power in Taiwan. Any IPP (Independent Power Producer) or power trading platform that can provide stable solar, wind, or geothermal power effectively becomes part of the TSMC supply chain.

Part Seven: Conclusion and Recommendations — Standing on the Shoulders of Giants, Embracing the "Inevitable" Future

1. Historical Positioning: The "General Electric (GE)" of the AI Era

Looking back at the Industrial Revolution, oil, steel, and electricity were the fundamental energies driving the world. In the Fourth Industrial Revolution brought about by AI, "Compute" is the new oil. And TSMC is the super drilling platform that controls 90% of the world's high-end compute extraction rights.

This 2025 Q4 earnings call was not just a financial report; it was a "declaration of hegemony." It tells the world:

• Technologically: Through A16 and SPR, the interpretation rights of Moore's Law are in TSMC's hands.
• Capital-wise: Through $56 billion in CapEx, the entry price for competition has been raised to an astronomical level unaffordable by competitors.
• Ecologically: From the cloud (Microsoft) to the edge (Apple), all AI pathways ultimately converge at wafer fabs in Taiwan.

Therefore, we should no longer view TSMC as a mere "electronics contract manufacturer," but should reprice it as a "monopolistic operator of global AI infrastructure." Its business model is closer to Visa (payments), Google (search), or early GE (power), possessing strong utility-like characteristics and growth potential.

2. Valuation Paradigm Shift

Investors often ask: "Is TSMC expensive now?" If viewed through the lens of past smartphone cycles (P/E 15-20x), perhaps not cheap. But if viewed through an AI infrastructure mindset (PEG / DCF), TSMC remains undervalued:

• Growth: Large enterprises with revenue CAGR of 20-30% are few and far between globally.
• Certainty: Order visibility extends to 2028, with extremely low profit volatility risk.
• Moat: A monopolistic position with virtually no substitutes.

We believe the market will eventually grant TSMC a re-rating, elevating its P/E multiple range to levels comparable with major US software giants or AI platform stocks.

3. Ultimate Investment Strategy: Core & Satellite

In this decade-long AI feast, we recommend investors adopt the following allocation strategy:

A. The Core: TSMC Itself

• Strategy: "Buy and Hold."
• Mindset: View TSMC as the "stabilizer" in your investment portfolio. Disregard quarterly inventory adjustments or short-term revenue noise. As long as the A16 mass production progress and gross margin structure remain unchanged, hold firm.
• Action: Any stock price pullback (Drawdown) caused by non-fundamental factors (such as geopolitical panic) is a gift from above for accumulation.

B. The Satellite: Supply Chain Alpha

• Strategy: "Swing Trading and Thematic Investing."
• Target Selection:
  • Aggressive: Focus on CoWoS equipment stocks and CPO (Silicon Photonics) concept stocks. These small and medium-cap stocks have the highest explosive potential but are highly volatile.
  • Conservative: Focus on consumables (mask pods/chemicals) and heavy electrical/green energy stocks. These stocks offer stable yields and long-term growth.
• Action: Dynamically adjust the proportion of these satellite holdings based on TSMC's monthly revenue announcements and capital expenditure progress.

4. A Message to Investors

CEO C.C. Wei said: "AI is Real." We would like to add: "TSMC's monopoly is also real."

In this world full of uncertainties, TSMC offers a scarce asset—"certainty about the future." Investing in TSMC is investing in humanity's endless craving for compute power. This is a high-probability game that has just begun.