Semiconductor

/ 125 posts

The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

Insight Semiconductor
What's New?
3-3 Data Skyscraper —— The Magic of 3D NAND and Controller Chips
Semiconductor
EDGE / / 9 minutes read

3-3 Data Skyscraper —— The Magic of 3D NAND and Controller Chips

3D NAND vertical stacking breaks capacity bottlenecks; Lam Research's high-aspect-ratio etching is critical. QLC, for AI storage, mitigates inherent flaws via controller algorithms. aiDAPTIV+ extends SSDs into computational units, reshaping the AI storage value chain.
3-2 Edge Warriors —— LPDDR5X, DDR5, and CAMM2 Revolution
Semiconductor
EDGE / / 6 minutes read

3-2 Edge Warriors —— LPDDR5X, DDR5, and CAMM2 Revolution

Edge AI needs speed, power, thinness. LPDDR5X soldered for integrity, not expandable. LPCAMM2, 20-year laptop revolution, modularizes LPDDR into thin, high-bandwidth, power-efficient, serviceable board, AI PC standard. This helps Taiwan's UMT & connector makers shift to high-margin precision comp...
3-1 The Lifeblood of AI —— HBM, TSV, and SK Hynix's Resurgence
Semiconductor
EDGE / / 9 minutes read

3-1 The Lifeblood of AI —— HBM, TSV, and SK Hynix's Resurgence

HBM vertically stacks DRAM via TSV to overcome GDDR bandwidth. SK Hynix's MR-MUF solved thermals, beating Samsung's TC-NCF for AI chip dominance. For HBM4's 16-layer limit, Wuxi Ball's hybrid bonding is standard. TSMC intervenes in bottom manufacturing, becoming ultimate co-leader in memory packa...
3-0 The Famine of Computing Power —— Overcoming the Desperate 'Memory Wall'
Semiconductor
EDGE / / 5 minutes read

3-0 The Famine of Computing Power —— Overcoming the Desperate 'Memory Wall'

Logic chip power surges, memory lags, forming a fatal 'memory wall.' Massive AI models spark a bandwidth crisis: data movement power exceeds computation, yielding 'data transport tax' & computing famine. Industry initiates revolution via HBM stacking & CXL, igniting bandwidth war reshaping global...
2-7-3 The Battle of Approaches — Intel PowerVia vs. TSMC SPR
Semiconductor
EDGE / / 8 minutes read

2-7-3 The Battle of Approaches — Intel PowerVia vs. TSMC SPR

Backside power sparks an architectural gamble. Intel's PowerVia routes power to front M0 (debug-friendly, less scaling). TSMC's A16 SPR sends power direct to bottom S/D, seeking performance. Extreme alignment aside, frees front space for ultimate scaling, ensuring strongest PPA.
2-7-2 — Extreme Engineering — Wafer Backside Refinement
Semiconductor
EDGE / / 6 minutes read

2-7-2 — Extreme Engineering — Wafer Backside Refinement

BPD relies on extreme wafer-flipping: temp carrier support; DISCO grinds 99% Si to micron thickness; IR alignment etches nano TSVs for front contacts; low-temp backside power layer deposition. This micro-refinement sparks huge opportunities for semi equipment makers.