Semiconductor

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The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

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2-6-2 Construction Technique —— How to Build a Suspended Nanobuilding?
Semiconductor
EDGE / / 6 minutes read

2-6-2 Construction Technique —— How to Build a Suspended Nanobuilding?

GAA is nanoscale Jenga. Epitaxially stacking Si/SiGe builds framework; trenches cut. Lam Research's "selective etching" removes SiGe sacrificial layers, suspending Si nanosheets. ASMI's ALD fills metal gates in narrow gaps. Gravity-defying, it challenges GAA yield.
2-6-3 A Bet of the Century — Samsung's Waterloo, TSMC's N2 and CFET
Semiconductor
EDGE / / 7 minutes read

2-6-3 A Bet of the Century — Samsung's Waterloo, TSMC's N2 and CFET

Samsung rushed 3nm GAA to overtake, but suffered Waterloo due to low etching yield & immature ecosystem. TSMC maximized FinFET, secured high-yield orders, steadily introduced 2nm GAA, proving mature ecosystem true moat. 1nm angstrom transistors will adopt vertically stacked P/N CFET, initiating f...
2-7-0 The Energy Crisis of Compute Buildings —— When a Super-Powered Faucet Meets a Clogged Sewer
Semiconductor
EDGE / / 4 minutes read

2-7-0 The Energy Crisis of Compute Buildings —— When a Super-Powered Faucet Meets a Clogged Sewer

GAA hasn't solved chip scaling's wiring congestion: traditional top-side power/signal causes IR Drop near 2nm, limiting performance. Backside Power Delivery Network (BSPDN) moves power to wafer's backside, separating power/signals. This engineering is critical for TSMC A16 vs. Intel 18A.
2-7-1 Physical Predicament — When the Building's Elevators Are Overwhelmed
Semiconductor
EDGE / / 7 minutes read

2-7-1 Physical Predicament — When the Building's Elevators Are Overwhelmed

Traditional front-side power delivery crowds signals & power, causing crises: thick lines take >20% space, hindering miniaturization; current via ultra-thin wires causes severe IR Drop, degrading performance & heat. The sole solution is to move the power delivery network to the wafer backside, fu...
2-7-2 — Extreme Engineering — Wafer Backside Refinement
Semiconductor
EDGE / / 6 minutes read

2-7-2 — Extreme Engineering — Wafer Backside Refinement

BPD relies on extreme wafer-flipping: temp carrier support; DISCO grinds 99% Si to micron thickness; IR alignment etches nano TSVs for front contacts; low-temp backside power layer deposition. This micro-refinement sparks huge opportunities for semi equipment makers.
2-7-3 The Battle of Approaches — Intel PowerVia vs. TSMC SPR
Semiconductor
EDGE / / 8 minutes read

2-7-3 The Battle of Approaches — Intel PowerVia vs. TSMC SPR

Backside power sparks an architectural gamble. Intel's PowerVia routes power to front M0 (debug-friendly, less scaling). TSMC's A16 SPR sends power direct to bottom S/D, seeking performance. Extreme alignment aside, frees front space for ultimate scaling, ensuring strongest PPA.