2-7-0 The Energy Crisis of Compute Buildings —— When a Super-Powered Faucet Meets a Clogged Sewer
GAA hasn't solved chip scaling's wiring congestion: traditional top-side power/signal causes IR Drop near 2nm, limiting performance. Backside Power Delivery Network (BSPDN) moves power to wafer's backside, separating power/signals. This engineering is critical for TSMC A16 vs. Intel 18A.
2-6-3 A Bet of the Century — Samsung's Waterloo, TSMC's N2 and CFET
Samsung rushed 3nm GAA to overtake, but suffered Waterloo due to low etching yield & immature ecosystem. TSMC maximized FinFET, secured high-yield orders, steadily introduced 2nm GAA, proving mature ecosystem true moat. 1nm angstrom transistors will adopt vertically stacked P/N CFET, initiating f...
2-6-2 Construction Technique —— How to Build a Suspended Nanobuilding?
GAA is nanoscale Jenga. Epitaxially stacking Si/SiGe builds framework; trenches cut. Lam Research's "selective etching" removes SiGe sacrificial layers, suspending Si nanosheets. ASMI's ALD fills metal gates in narrow gaps. Gravity-defying, it challenges GAA yield.
2-6-1 Structural Evolution Theory —— Why Can't the Faucet Be Shut Off Tightly?
Transistor scaling caused quantum leakage, failing 2D architecture. TSMC's 3D FinFET dominated 16-3nm. At 2nm, FinFET hit physical limits, forcing a shift to GAA (Gate-All-Around). GAA, via suspended nanosheets, provides 360° perfect control, fully resolving leakage, offering channel width flexib...
The Limits of the 2-6-0 Blueprint — When Tools Cannot Overcome Physical Laws
As process technology nears 3nm, upgrading advanced equipment alone can't save Moore's Law. Transistor gates thinned to atomic scale trigger the "quantum tunneling effect," causing severe leakage and heat. Facing physical limits, fabs must fundamentally rebuild their architecture, moving from 2D ...
2-5-4 The Art of Quality Control —— Inspection and Metrology
Wafer quality control entails dimension measurement & defect inspection. KLA built deep front-end barriers via its yield database, dominating over 50% market share as 'semiconductor landlord.' CoWoS packaging sparked a back-end inspection revolution, with 3D micro-solder ball inspection demand su...
2-5-3 The Art of Change —— Ion Implantation and CMP Planarization
Pure silicon undergoes ion implantation for impurity introduction and thermal annealing for lattice repair. AMAT dominates standard processes; Axcelis monopolizes SiC automotive. CMP planarization flattens wafers, solving photolithography focus issues and is core to CoWoS packaging. AMAT solely d...
[Industry Capital Flows Weekly] 20260215 Capitalizing on AI Specification Bonuses, Avoiding Equipment Makers' Book-Closing Sell-off
This week, large funds prioritize 'selective strengthening and intertemporal allocation'. Amid high index volatility, Smart Money heavily targets 'AI infrastructure' and 'semiconductor cycle recovery' supply chains. Overvalued, fundamentally weak sub-sectors face ruthless liquidation. Capital rap...
2-5-1 The Art of Addition — Thin Film Deposition and ALD Mastery
Deposition builds chip conductive/insulating layers. PVD (physical sputtering, AMAT-led); CVD (gas chemical films); ALD (2nm processes, single-atom LBL, perfect 3D encap, boosts ASMI). Copper fill: Lam Research. AMAT 'King of Addition', ALD future core.