Semiconductor

/ 125 posts

The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

What's New?
EDGE / / 3 minutes read

5-1-11 The Final Battle: The Red Wolf Pack Under the City Walls and a Panoramic Map of Semiconductor Packaging

Semiconductor packaging & testing competition analyzed. Chinese 'red-chip' firms (JCET, Tongfu, Unisilicon) challenge traditional giants via asymmetric strategies. Tech mapping from traditional to 3D heterogeneous integration shows packaging evolving to extend Moore's Law via 'brain surgery.' Thi...
EDGE / / 20 minutes read

5-2-1 CoWoS Architecture Universe: Photomask Limits and TSMC's Process Magic

TSMC's CoWoS resolves AI chip bottlenecks, tackling thick substrate signal loss. It uses silicon interposers as micro-highways for high-density TSV/lithography. The article details CoW/oS processes, explaining TSMC's high-value dominance and substrate assembly outsourcing. This precision engineer...
EDGE / / 10 minutes read

5-2-3 The Extremes of Wet Cleaning and Tape Peeling: Wet Process Giants Grand Plastic (3131) vs. Scientech (3583)

Wet processes are key semiconductor expansion indicators. Grand Plastic (3131) uses TSMC's CoWoS-L for advanced packaging. Scientech (3583) uses TB/DB tech on thin wafer fragility. Both dominate cleaning/thin wafer processing bottlenecks, indispensable AI equipment giants.
EDGE / / 9 minutes read

5-2-5 The Physical Curse of Grilled Squid and Synergistic Light-Heat Strategy: Stress Release GPM (2467) vs. Zero-Pressure Laser T-Laser (8027)

GPM's VPO oven resolves CoWoS wafer warpage (material CTE diffs) via stress release, solving 'grilled squid' curse. Its G2C+ alliance provides local R&D for TSMC processes. For WMCM/3D stacking, GPM became an advanced packaging supplier, building a deep ecosystem moat.
EDGE / / 10 minutes read

5-2-6 CoWoS's Hidden Defense Line: The US-Japan Chemical Chokehold Battle and Wah Lee (3010), Hong Teng (7751)'s Cutting-Edge Thermal Management Technology

US/Japan monopolize CoWoS packaging's underfill & TIMs, essential for AI chip stability, thermal limits, and yield. Distributors like Wah Lee & Chang Hwa, with strict cold chain & local support, build moats as indispensable advanced process gatekeepers, given high replacement costs.
EDGE / / 10 minutes read

5-3-1 SoIC 3D Packaging Showdown: AMD's 3D Trump Card for a Counterattack Against NVIDIA and Besi's Bumpless Dominance

Analyzing TSMC's SoIC hybrid bonding, achieving atom-level fusion to break traditional 3D packaging bottlenecks. Contrasting NVIDIA's heat-first 2.5D with AMD's 3D stacking performance push; Besi's bumpless tech edge is highlighted. As planar packaging nears limits, 3D structures will be critical...