Semiconductor

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The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

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5-2-5 The Physical Curse of Grilled Squid and Synergistic Light-Heat Strategy: Stress Release GPM (2467) vs. Zero-Pressure Laser T-Laser (8027)
Semiconductor
EDGE / / 9 minutes read

5-2-5 The Physical Curse of Grilled Squid and Synergistic Light-Heat Strategy: Stress Release GPM (2467) vs. Zero-Pressure Laser T-Laser (8027)

GPM's VPO oven resolves CoWoS wafer warpage (material CTE diffs) via stress release, solving 'grilled squid' curse. Its G2C+ alliance provides local R&D for TSMC processes. For WMCM/3D stacking, GPM became an advanced packaging supplier, building a deep ecosystem moat.
5-2-4 Die Bonder: The Ultimate Micron Showdown – Global Hegemons vs. Taiwan's Wonbond (6187) and Jinhua (6640) Carving Out Their Niche
Semiconductor
EDGE / / 15 minutes read

5-2-4 Die Bonder: The Ultimate Micron Showdown – Global Hegemons vs. Taiwan's Wonbond (6187) and Jinhua (6640) Carving Out Their Niche

Die bonder challenges in packaging: Surging AI chip value mandates micron-precision thermocompression bonding, high barriers. Dutch Besi (hybrid bonding) & HK's ASMPT (advanced packaging) dominate. Taiwan's Wonbond and Jinhua seek niche breakthroughs, vying with foreign hegemons for packaging.
5-2-3 The Extremes of Wet Cleaning and Tape Peeling: Wet Process Giants Grand Plastic (3131) vs. Scientech (3583)
Semiconductor
EDGE / / 10 minutes read

5-2-3 The Extremes of Wet Cleaning and Tape Peeling: Wet Process Giants Grand Plastic (3131) vs. Scientech (3583)

Wet processes are key semiconductor expansion indicators. Grand Plastic (3131) uses TSMC's CoWoS-L for advanced packaging. Scientech (3583) uses TB/DB tech on thin wafer fragility. Both dominate cleaning/thin wafer processing bottlenecks, indispensable AI equipment giants.
The 5-2-2 HBM Stacking Crucible: The MR-MUF Crusade and Powertech Technology (6239)'s Sparkling Water Strategy
Semiconductor
EDGE / / 15 minutes read

The 5-2-2 HBM Stacking Crucible: The MR-MUF Crusade and Powertech Technology (6239)'s Sparkling Water Strategy

Analyzing HBM packaging challenges (thermal leakage, high-temp warpage in ultra-thin stacking), contrasting Samsung's precise but inefficient TC-NCF (causing yield bottlenecks) with SK Hynix's breakthrough MR-MUF, a 'holy war' at physical limits crucial for product yield and memory giants' AI-era...
5-2-1 CoWoS Architecture Universe: Photomask Limits and TSMC's Process Magic
Semiconductor
EDGE / / 20 minutes read

5-2-1 CoWoS Architecture Universe: Photomask Limits and TSMC's Process Magic

TSMC's CoWoS resolves AI chip bottlenecks, tackling thick substrate signal loss. It uses silicon interposers as micro-highways for high-density TSV/lithography. The article details CoW/oS processes, explaining TSMC's high-value dominance and substrate assembly outsourcing. This precision engineer...
5-1-11 The Final Battle: The Red Wolf Pack Under the City Walls and a Panoramic Map of Semiconductor Packaging
Semiconductor
EDGE / / 3 minutes read

5-1-11 The Final Battle: The Red Wolf Pack Under the City Walls and a Panoramic Map of Semiconductor Packaging

Semiconductor packaging & testing competition analyzed. Chinese 'red-chip' firms (JCET, Tongfu, Unisilicon) challenge traditional giants via asymmetric strategies. Tech mapping from traditional to 3D heterogeneous integration shows packaging evolving to extend Moore's Law via 'brain surgery.' Thi...