Semiconductor

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The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

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2-5-2 The Art of Subtraction — Etching and Cleaning
Semiconductor
EDGE / / 5 minutes read

2-5-2 The Art of Subtraction — Etching and Cleaning

Semiconductor etching, or "subtraction," is Lam Research's domain. Advanced processes use precise dry plasma etching. Lam's HAR & ALE are key for 3D NAND/GAA. Post-etch cleaning is critical: TEL dominates front-end. Hermes-Epitek & Scientech dominate CoWoS back-end cleaning, seizing market.
2-5-1 The Art of Addition — Thin Film Deposition and ALD Mastery
Semiconductor
EDGE / / 5 minutes read

2-5-1 The Art of Addition — Thin Film Deposition and ALD Mastery

Deposition builds chip conductive/insulating layers. PVD (physical sputtering, AMAT-led); CVD (gas chemical films); ALD (2nm processes, single-atom LBL, perfect 3D encap, boosts ASMI). Copper fill: Lam Research. AMAT 'King of Addition', ALD future core.
2-5-3 The Art of Change —— Ion Implantation and CMP Planarization
Semiconductor
EDGE / / 11 minutes read

2-5-3 The Art of Change —— Ion Implantation and CMP Planarization

Pure silicon undergoes ion implantation for impurity introduction and thermal annealing for lattice repair. AMAT dominates standard processes; Axcelis monopolizes SiC automotive. CMP planarization flattens wafers, solving photolithography focus issues and is core to CoWoS packaging. AMAT solely d...
2-5-4 The Art of Quality Control —— Inspection and Metrology
Semiconductor
EDGE / / 8 minutes read

2-5-4 The Art of Quality Control —— Inspection and Metrology

Wafer quality control entails dimension measurement & defect inspection. KLA built deep front-end barriers via its yield database, dominating over 50% market share as 'semiconductor landlord.' CoWoS packaging sparked a back-end inspection revolution, with 3D micro-solder ball inspection demand su...
The Limits of the 2-6-0 Blueprint — When Tools Cannot Overcome Physical Laws
Semiconductor
EDGE / / 6 minutes read

The Limits of the 2-6-0 Blueprint — When Tools Cannot Overcome Physical Laws

As process technology nears 3nm, upgrading advanced equipment alone can't save Moore's Law. Transistor gates thinned to atomic scale trigger the "quantum tunneling effect," causing severe leakage and heat. Facing physical limits, fabs must fundamentally rebuild their architecture, moving from 2D ...
2-6-1 Structural Evolution Theory —— Why Can't the Faucet Be Shut Off Tightly?
Semiconductor
EDGE / / 7 minutes read

2-6-1 Structural Evolution Theory —— Why Can't the Faucet Be Shut Off Tightly?

Transistor scaling caused quantum leakage, failing 2D architecture. TSMC's 3D FinFET dominated 16-3nm. At 2nm, FinFET hit physical limits, forcing a shift to GAA (Gate-All-Around). GAA, via suspended nanosheets, provides 360° perfect control, fully resolving leakage, offering channel width flexib...