Semiconductor

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The EDGE Semiconductor Research Zone provides in-depth analysis of the global chip industry's complex supply chain, from FinFET to silicon photonics. We cover AI, geopolitics, and rapid tech iteration with continuously updated insights, empowering you to master critical variables and make informed decisions.

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5-1-10 OSAT Giants' Counterattack Defense Line: ASE Technology Holding (ASE) and Amkor's VIPack
Semiconductor
EDGE / / 10 minutes read

5-1-10 OSAT Giants' Counterattack Defense Line: ASE Technology Holding (ASE) and Amkor's VIPack

OSAT firms counter TSMC's lead & China's price wars. ASE builds a moat via LEAP/VIPack, with flexible capacity & heterogeneous integration. Amkor targets high-end auto/US clients; Powertech focuses on HBM. All shift to system integration, pursuing AI breakthroughs.
5-1-9 The Vanishing Boundaries of Business Warfare: TSMC's Dimension-Reduction Strike
Semiconductor
EDGE / / 7 minutes read

5-1-9 The Vanishing Boundaries of Business Warfare: TSMC's Dimension-Reduction Strike

TSMC's InFO blurs foundry/OSAT lines. Its nanoscale process launched a 'dimension-reduction strike,' eliminating substrates for ultra-thinness. Co-design linked front/back processes, overcame bottlenecks, built high tech barriers/customer stickiness, reshaping semiconductor competition.
5-1-8 The 'Disintegration' and Rebirth of Moore's Law: The Additive Magic of Chiplets and Yield
Semiconductor
EDGE / / 8 minutes read

5-1-8 The 'Disintegration' and Rebirth of Moore's Law: The Additive Magic of Chiplets and Yield

Moore's Law faces miniaturization's reticle/yield. Chiplet tech disassembles large chips; heterogeneous integration reassembles varied parts, yield additive (vs. mult.) cuts costs. AMD MI300 shows 3D packaging/UCIe key for post-Moore compute.
5-1-7 The Spatial Reversal: The Performance Revolution of RDL and Flip Chip (Flip Chip Packaging)
Semiconductor
EDGE / / 9 minutes read

5-1-7 The Spatial Reversal: The Performance Revolution of RDL and Flip Chip (Flip Chip Packaging)

Flip Chip's spatial reversal breaks wire bonding bottlenecks. RDL routes contacts from edge to interior; copper pillars connect directly to substrate, reducing latency, increasing bandwidth, optimizing cooling. Despite thermal expansion warping (needs underfill), it's crucial for AI chip compute ...
5-1-6 The Immortal Veteran and Its Limits: Lead Frame, Die Bond, and Wire Bond
Semiconductor
EDGE / / 10 minutes read

5-1-6 The Immortal Veteran and Its Limits: Lead Frame, Die Bond, and Wire Bond

Lead frame packaging status. Advanced packaging a focus, but 80% of chips rely on cost-effective lead frames. Taiwan's 'Three Musketeers' (Shuen De, Chang Wah Electromaterials, Jielin) solidify market via metallurgy, M&A, power modules. Die/wire bond challenges. Efficiency/physical limits positio...
5-1-5 The Limits of Physical Dicing: From Mechanical Blades to Laser Stealth Dicing (Stealth Dicing)
Semiconductor
EDGE / / 7 minutes read

5-1-5 The Limits of Physical Dicing: From Mechanical Blades to Laser Stealth Dicing (Stealth Dicing)

Semiconductor dicing examined: traditional blades cause Low-k material chipping and thinned wafer yield issues. Laser stealth dicing achieves precise separation via internal modification/tape expansion, solving these. Consumables market analyzed; Taiwanese firm Titan Speech excels in advanced pac...